Semiconductor components, such as chip scale packages, are being made thinner and smaller than previous generation components. At the same time, electrical and packaging requirements for semiconductor components are becoming more stringent. One challenge during fabrication of semiconductor components is the alignment of elements on the back side of a semiconductor substrate to elements on the circuit side. For example, conductive vias interconnect circuit side elements, such as circuit side conductors and bond pads, to back side elements, such as back side conductors and terminal contacts. The conductive vias are becoming smaller, such that conventional fabrication processes for aligning the conductive vias to back side elements are becoming more difficult.
FIGS. 1A-1E illustrate a semiconductor fabrication process in which the alignment of conductive vias in a semiconductor substrate to back side features on the substrate is an issue. As shown in FIG. 1A, a semiconductor wafer 10 includes a plurality of semiconductor substrates 12, such as semiconductor dice. The semiconductor wafer 10, and each of the semiconductor substrates 12 as well, include a circuit side 16 and a back side 18. In addition, each semiconductor substrate 12 includes a plurality of conductive vias 14 extending from circuit side 16 to the back side 18 thereof. Each conductive via 14 comprises a through via 20 in the semiconductor substrate 12 lined with a via insulator 22 and filled with a conductive metal.
As also shown in FIG. 1A, each semiconductor substrate 12 also includes a plurality of redistribution conductors 24 on the circuit side 16 in electrical communication with the conductive vias 14. The redistribution conductors 24 are insulated from the semiconductor substrate 12 by an inner dielectric layer 26, and are covered by an outer dielectric layer 28. The wafer 10 is attached to a wafer carrier 30 using a carrier adhesive 32, which permits back side fabrication processes, such as back side thinning and planarization, to be performed. These processes planarize the substrate 12, and form planarized contactors 42 (FIG. 1A) on the ends of the conductive vias 14. The wafer carrier 30 also allows other processes to be performed, such as the formation of back side elements (e.g., terminal contacts). In the present case, a photo patterning process is being performed to form back side conductors 34 in electrical communication with the conductive vias 14.
As shown in FIG. 1B, the photo patterning process is initiated by depositing a layer of resist 36 on the back side 18 of the wafer 10. The layer of resist 36 can be deposited using a conventional process such as spin coating. Next, as shown in FIG. 1C, the layer of resist 36 can be exposed and developed to form a photo mask 38 on the back side 18 of the wafer 10. The photo mask 38 includes a plurality of openings 40 which should align with the exposed contactors 42 on the conductive vias 14. Alignment can be achieved using alignment marks on the circuit side 16 and on the back side 18 of the wafer 10. However, due to the size of the conductive vias 14 and the size of the openings 40, and the limitations of conventional photo exposure equipment, alignment can be difficult to achieve. As shown in FIG. 2A, in order to facilitate alignment, the conductive vias 14 can be made larger than the openings 40 (represented by dotted lines in FIG. 2A) in the photo mask 38. For example, the conductive vias 14 can have an inside diameter (ID) of about 18 μm, and the openings 40 in the photo mask 38 can have a diameter (OD) of about 11 μm. This allows misalignment of about 3.5 μm on each side of the conductive vias 14 to occur.
FIG. 2A illustrates the optimal alignment situation wherein the centers of the conductive vias 14 and the centers of the openings 40 are in perfect alignment. However, as shown in FIG. 2B, in actual practice, the openings 40 in the photo mask 38 does not perfectly align with the conductive vias 14. As will be further explained, this situation can cause short circuits 44 (FIG. 2D) to form between the conductors 34 (FIG. 2D) and the substrate 12. As shown in FIG. 2C, the openings 40 in the photo mask 38 may completely miss the conductive vias 14. As will be further explained, this situation can form open circuits.
As shown in FIG. 1D, following formation of the photo mask 38, the contactors 42 can be etched to remove contaminants and native oxide layers. Next, as shown in FIG. 1E, the conductors 34 can be formed in the openings 40 using a process such as electroless deposition. The conductors 34 can comprise a highly conductive metal such as copper. As also shown in FIG. 1E, under bump metallization layers 46, 48 for terminal contacts (not shown) can be formed on the conductors 34. The under bump metallization layers 46, 48 can be formed using a suitable process such as electroless deposition out of suitable metals.
FIGS. 2D and 2E illustrate potential problems caused by misalignment of the conductors 34 to the conductive vias 14. As shown in FIG. 2D, misalignment by a small amount (e.g., <5 μm) can cause short circuits 44 between the conductors 34 and the semiconductor substrate 12. As shown in FIG. 2E, misalignment by a large amount (e.g., >9 μm) can cause an open circuit between the conductor 34 and the conductive via 14.
In view of the foregoing, improved methods for fabricating semiconductor components with back side elements are needed in the art. However, the foregoing examples of the related art and limitations related therewith, are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent to those of skill in the art upon a reading of the specification and a study of the drawings.